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Chapter 5 LC-3

ISA

ISA Tells programmers how to write machine language.

instruction set specifies:

instruction:

Overview

LC-3: memory 216βˆ’byβˆ’16bits2^{16} -by-16 bitsο»Ώ

address space = 64K, addressability = 16 bits (size of each memory location)

Registers: TEMP, temporary storage (access time of registers is much shorter than that of memory)

GPR (general purpose register): R0-R7, 3-bit to identify their number, each 16 bits wide

Opcodes:

Condition code setting instructions (these instructions write values into registers, based on the last instruction that altered a register): LD, LDI, LDR, ADD, AND, NOT

Data type:

16-bit 2’s complement integer

Addressing mode:

Operate instructions

ADD, AND, NOT

NOT

In the processing unit

ALU + REG FILE (TEMP)

P704, REG FILE (src) β†’ SR1 OUT β†’ ALU β†’ GateALU β†’ Processing bus β†’ REG FILE (dst)

ADD / AND

(DR, SR1, SR2)

See P704, SR2MUX is selected by IR[5], specifying whether use imm5 or SR2.

Data Movement Instructions

The location of the destination operand is over written with the source operand.

load

data: register ← memory

LD: PC-relative, PCoffset9, βˆ’256≀offset9≀+255-256 \le offset9 \le +255ο»Ώ,

LDR: base + offset

LDI: indirect, read address from memory location and load / store that address

Note: PC incremented is done in FETCH, which is before the EVALUATE ADDRESS stage.

LD:

P704, IR β†’ SEXT[8:0] β†’ ADDR2MUX + ADDR1MUX (PC) β†’ MARMUX β†’ GateMARMUX β†’ MAR β†’ Memory β†’ MDR β†’ GateMDR β†’ REG FILE (dst) + condition code

LDI:

IR β†’ SEXT[8:0] β†’ ADDR2MUX + ADDR1MUX (PC) β†’ MARMUX β†’ Processor Bus β†’ MAR β†’ Memory β†’ MDR (for this time, it contains an address (value) for the next interrogate) β†’ GateMDR β†’ processor bus β†’ MAR (that value as the new address) β†’ Memory β†’ MDR β†’ GateMDR β†’ processor bus β†’ REG FILE

LDR

IR β†’ SEXT[5:0] β†’ ADDR2MUX + ADDR1MUX (SR1, instead of PC) β†’ MARMUX β†’ GateMARMUX β†’ processor unit β†’ MAR β†’ Memory β†’ MDR β†’ GateMDR β†’ REG FILE (DR)

store

data: register β†’ memory

ST: PC-relative

STR: base + offset

STI: indirect

Note: to store a value in a memory location, you should have both the address (in MAR) and the value (in MDR).

ST:

Compared to LD, the MDR is reversed.

STI: P704

IR β†’ SEXT[8:0] β†’ ADDR2MUX + ADDR1MUX (PC) β†’ MARMUX β†’ GateMARMUX β†’ Processor bus β†’ MAR β†’ Memory β†’ MDR β†’ Processor bus β†’ MAR (as an address to store the value)

Src β†’ MDR

Access the memory and write that value in MDR to that memory location.

STR:

IR β†’ SEXT[5:0] β†’ ADDR2MUX + ADDR1MUX (BaseR) β†’ MARMUX β†’ GateMARMUX β†’ processor unit β†’ MAR β†’ Memory

Src (REG FILE) β†’

LEA

Load effective address, load / compute the address (specified by PCoffset9) value and store the value into DR.

It doesn’t read memory and doesn’t set condition codes. (No MAR and MDR)

It is not added in ALU. ALU only implements operation (ADD, NOT, AND) from REG FILE or immediate number.

IR β†’ SEXT[8:0] β†’ ADDR2MUX + ADDR1MUX (PC) β†’ Get the effective address β†’ MARMUX β†’ GateMARMUX β†’ processor bus β†’ REG FILE (Dst)

Control Instructions

TRAP

service call, the called service routine is specified by trapvector8

BR

Conditional branch

Take condition code registers’ value as control signal of PCMUX

The address of the next instruction PC = PC (has incremented) + offset9

Methods of loop control:

JMP

REG FILE β†’ SR1 OUT β†’ ALU β†’ GateALU β†’ processor bus β†’ PCMUX

Data Path (Revisited) P175

Global Bus

Consist of 16 wires, allowing one structure to transfer up to 16 bits of information to another structure. Exactly one value (word) can be transferred over the global bus.

Any components can read the global bus.

Tristate device: The input arrow into the global bus always follows a not filled-in triangle, allowing the computer’s control logic to enable exactly one supplier to provide information to the bus at any one time. See GateMARMUX, GateMDR… in P704.

Register only captures the data from the global bus if it’s write-enabled by the control unit.

The structure wishing to obtain the value being supplied can do so by asserting its LD.x (load enable) signal (similar to write enable in Gated D Latch).

See LD.REG, LD.PC, LD.MDR, LD.MAR… in P704.

Memory

ALU

AND, ADD, NOT (in LC-3)

ALU only accepts values from REG FILE (SR1, SR2) or SEXT immediate numbers(SR2).

Which to choose is determined by select line of the SR2MUX (IR[5], control signal).

Register File

Two read addresses (SR1, SR2), one write addresses (DR).

Input only from global bus (from ALU / REG FILE or memory read (LD)).

Data for storing in the memory passes through ALU.

STR, store the value of the register into MDR, then into memory.

PC, PCMUX

(MAR ← PC) At the start of each instruction cycle, PC is supplied to MAR over global bus.

PCMUX: (left to right)

MAR, MARMUX

Two inputs:

Condition Code Logic

Looks at value on the bus to determine N, Z, P.

Only set when LD.CC enables them (instructions: LD, LDI, LDR, ADD, AND, NOT)

Control Unit - Finite State Machine

Provide control signals for the machine cycle.

Load enable (LD.REG…) is aimed at registers.

Instruction Cycle of LC-3

Note: ADD, AND, NOT don’t need EVALUATE ADDRESS; LD, LDI, LDR don’t need EXECUTE.